TY - GEN
T1 - Fe-GCN
T2 - 26th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023
AU - Zhong, Hongtao
AU - Zhu, Yu
AU - Luo, Longfei
AU - Li, Taixin
AU - Wang, Chen
AU - Xu, Yixin
AU - Wang, Tianyi
AU - Yu, Yao
AU - Narayanan, Vijaykrishnan
AU - Liu, Yongpan
AU - Shi, Liang
AU - Yang, Huazhong
AU - Li, Xueqing
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Graph convolutional network (GCN) has emerged as a powerful model for many graph-related tasks. In conventional von Neumann architectures, massive data movement and irregular memory access in GCN computation severely degrade the performance and computation efficiency. For GCN acceleration, processing-in-memory (PIM) is promising by reducing the data movement. However, with the emergence of large GCN computation tasks, existing 2D PIM GCN accelerators face the challenge of storing all the necessary data on chip due to the limited PIM memory capacity, resulting in unwanted external memory access and degradation of performance and energy efficiency. This paper presents Fe-GCN, a 3D PIM GCN accelerator with high memory density based on the ferroelectric field-effect transistor (FeFET) memory. Besides, to mitigate the impact of the increased latency of the 3D memory structure, several software-hardware co-optimizations are proposed. Furthermore, an edge merging technique is also proposed to increase the memory utilization for the 3D GCN mapping and computing. Experimental results show that Fe-GCN achieves on average 2,647x, 58x, 18x, and 35x speedup and 26,708x, 1,246x, 25x, and 57x energy efficiency improvement over CPU, GPU, the state-of-the-art accelerators based on RRAM PIM and ASIC, respectively.
AB - Graph convolutional network (GCN) has emerged as a powerful model for many graph-related tasks. In conventional von Neumann architectures, massive data movement and irregular memory access in GCN computation severely degrade the performance and computation efficiency. For GCN acceleration, processing-in-memory (PIM) is promising by reducing the data movement. However, with the emergence of large GCN computation tasks, existing 2D PIM GCN accelerators face the challenge of storing all the necessary data on chip due to the limited PIM memory capacity, resulting in unwanted external memory access and degradation of performance and energy efficiency. This paper presents Fe-GCN, a 3D PIM GCN accelerator with high memory density based on the ferroelectric field-effect transistor (FeFET) memory. Besides, to mitigate the impact of the increased latency of the 3D memory structure, several software-hardware co-optimizations are proposed. Furthermore, an edge merging technique is also proposed to increase the memory utilization for the 3D GCN mapping and computing. Experimental results show that Fe-GCN achieves on average 2,647x, 58x, 18x, and 35x speedup and 26,708x, 1,246x, 25x, and 57x energy efficiency improvement over CPU, GPU, the state-of-the-art accelerators based on RRAM PIM and ASIC, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85172077452&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85172077452&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI59464.2023.10238622
DO - 10.1109/ISVLSI59464.2023.10238622
M3 - Conference contribution
AN - SCOPUS:85172077452
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
BT - 2023 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023 - Proceedings
A2 - Kastensmidt, Fernanda
A2 - Reis, Ricardo
A2 - Todri-Sanial, Aida
A2 - Li, Hai
A2 - Metzler, Carolina
PB - IEEE Computer Society
Y2 - 20 June 2023 through 23 June 2023
ER -