TY - GEN
T1 - Ferroelectric Transistor based Non-Volatile Flip-Flop
AU - Wang, Danni
AU - George, Sumitha
AU - Aziz, Ahmedullah
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
AU - Gupta, Sumeet K.
N1 - Publisher Copyright:
© 2016 ACM.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2016/8/8
Y1 - 2016/8/8
N2 - We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40% - 50% smaller backup delay, 27% - 40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.
AB - We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40% - 50% smaller backup delay, 27% - 40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.
UR - http://www.scopus.com/inward/record.url?scp=85019647266&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85019647266&partnerID=8YFLogxK
U2 - 10.1145/2934583.2934603
DO - 10.1145/2934583.2934603
M3 - Conference contribution
AN - SCOPUS:85019647266
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 10
EP - 15
BT - ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016
Y2 - 8 August 2016 through 10 August 2016
ER -