TY - GEN
T1 - First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3D Ferroelectric Capacitor Memory
AU - Deng, Shan
AU - Xiao, Yi
AU - Jiang, Zhouhang
AU - Qin, Yixin
AU - Zhao, Zijian
AU - Zhang, Renzheng
AU - Howe, John
AU - Lee, Yushan
AU - Duan, Jiahui
AU - Joshi, Rajiv
AU - Kampfe, Thomas
AU - Luo, Tengfei
AU - Hou, Tuo Hung
AU - Gong, Xiao
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In this work, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectric-metal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; v) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for VW/2 scheme and worsens the VW/3 scheme as disturb increases to intolerable 2VW/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (CZ).
AB - In this work, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectric-metal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; v) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for VW/2 scheme and worsens the VW/3 scheme as disturb increases to intolerable 2VW/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (CZ).
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U2 - 10.1109/IEDM50854.2024.10873477
DO - 10.1109/IEDM50854.2024.10873477
M3 - Conference contribution
AN - SCOPUS:86000023354
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2024 IEEE International Electron Devices Meeting, IEDM 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Electron Devices Meeting, IEDM 2024
Y2 - 7 December 2024 through 11 December 2024
ER -