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Forensics of Error Rates of Quantum Hardware

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The qubit technologies, basis gate set, noise behavior, speed and coupling architecture are among the various factors that vary among various backends. Although third-party cloud providers offering quantum hardware as a service offer lower cost and flexibility to the users to choose from several qubit technologies, quantum hardware, and coupling maps; the actual execution of the program is not clearly visible to the customer. The success of the user program, in addition to various other metadata such as cost, performance, & number of iterations to converge, depends on the error rate of the backend used. Moreover, the third-party provider and/or tools (e.g., hardware allocator and mapper) may hold insider/outsider adversarial agents to conserve resources and maximize profit by running the quantum circuits on error-prone hardware. Thus it is important to gain visibility of the backend from various perspectives of the computing process e.g., execution, transpilation and outcomes. In this paper, we estimate the error rate of the backend from the original and transpiled circuit. Although many quantum services providers publish the error rates of their backends, we assume that such information may not be accurate and/or correspond to the actual hardware allocated to the program. For the forensics we propose two complementary approaches. First, we exploit the fact that qubit mapping and routing steps of the transpilation process select qubits and qubit pairs with low gate errors to minimize overall error accumulation. We leverage this to rank qubit links into bins and compare with publicly available data we are able to assign a bin rank within a difference of 2 with respect to the actual bin for upto 83.5% of the qubit links in IBM Sherbrooke and 80% in IBM Brisbane, 127 qubit IBM backends. Second, we derive the error rates of the backends from a pool of programs by solving fidelity equations using numerical nonlinear optimizer. We achieve upto 92.7% (97.3% ) accuracy for single qubit (2 qubit) gate error rates.

Original languageEnglish (US)
Title of host publicationProceedings - 2025 IEEE 43rd International Conference on Computer Design, ICCD 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages329-334
Number of pages6
ISBN (Electronic)9798331503468
DOIs
StatePublished - 2025
Event43rd International Conference on Computer Design, ICCD 2025 - Richardson, United States
Duration: Nov 10 2025Nov 12 2025

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Conference

Conference43rd International Conference on Computer Design, ICCD 2025
Country/TerritoryUnited States
CityRichardson
Period11/10/2511/12/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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