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Forensics of Transpiled Quantum Circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

There is a steady growth in research and demand for real quantum hardware in the Noisy Intermediate-Scale Quantum (NISQ) era of quantum computing. This prompts many third-party cloud providers to set up quantum hardware as a service that includes a wide range of qubit technologies and architectures to maximize performance at minimal cost. Different backends vary in terms of noise behavior, the basis gate set, coupling architecture and speed, among other factors. However, there is little to no visibility on where the execution of the circuit is actually taking place. The success of the user program is highly reliant on the backend that was used for execution. Besides, the third-party provider and/or tools (e.g., hardware mapper and allocator) may be untrustworthy and execute the quantum circuits on less efficient and more error-prone hardware to conserve resources and maximize profit. As such, gaining visibility on the backend from various aspects of the computing e.g., transpilation, execution and outcomes will be extremely valuable. Towards this goal, we introduce the problem of forensics in the domain of quantum computing where the objective is to trace the hardware and its properties where the quantum program has been transpiled and executed. Effective forensics can have many applications including establishing trust in the quantum cloud services. In this work, we focus on tracing the coupling map of the hardware (from the transpiled program) where the transpilation of the circuit took place. Next, we extracted the coupling map of the whole backend using as little as 3 transpiled circuits, both for user-based and transpiler-based (using auto-assignment feature) logical to physical mapping of the qubits. Finally, we addressed the problem of tracing the backends in a suite of backends using a pool of transpiled quantum circuits of varied sizes.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2025 - Proceedings of the Great Lakes Symposium on VLSI 2025
PublisherAssociation for Computing Machinery
Pages354-359
Number of pages6
ISBN (Electronic)9798400714962
DOIs
StatePublished - Jun 29 2025
Event35th Edition of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025 - New Orleans, United States
Duration: Jun 30 2025Jul 2 2025

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference35th Edition of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025
Country/TerritoryUnited States
CityNew Orleans
Period6/30/257/2/25

All Science Journal Classification (ASJC) codes

  • General Engineering

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