FPGA-based neuro-architecture intrusion detection system

A. A. Hassan, A. Elnakib, M. Abo-Elsoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

These Today's intrusion detection systems (IDSs) are playing an essential part of any network security system. A challenging task in designing such IDSs is the ability of detecting the system attacks at a high speed and with an acceptable accuracy. In this work, an IDS system is proposed and designed with two keys of success; its neuro-architecture, and the FPGA-based implementation of this architecture. The neuro-architecture of the proposed system provides not only system's capability of detecting attacks that are not included in the training sets, but also fast decision due to the natural parallelism propriety of the neural networks. Also, the software implementation of the proposed system is explained. Further more, an FPGA-based implementation of the system is illustrated to provide an extra enhancement of system speed. Besides, the FPGA-based implementation provides an improved scope of boosting security over the software-based system.

Original languageEnglish (US)
Title of host publication2008 International Conference on Computer Engineering and Systems, ICCES 2008
Pages268-273
Number of pages6
DOIs
StatePublished - 2008
Event2008 International Conference on Computer Engineering and Systems, ICCES 2008 - Cairo, Egypt
Duration: Nov 25 2008Nov 27 2008

Publication series

Name2008 International Conference on Computer Engineering and Systems, ICCES 2008

Conference

Conference2008 International Conference on Computer Engineering and Systems, ICCES 2008
Country/TerritoryEgypt
CityCairo
Period11/25/0811/27/08

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Hardware and Architecture
  • Software

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