Fully parallel digital implementation of connectionist associative memory

Kyusun Choi, William S. Adams

Research output: Contribution to journalConference articlepeer-review


In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.

Original languageEnglish (US)
Article number5727297
Pages (from-to)6.6.1-6.6.4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 1992
Event14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, United States
Duration: May 3 1992May 6 1992

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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