Fully parallel digital implementation of connectionist associative memory

Kyusun Choi; William S. Adams

doi:10.1109/CICC.1992.591144

Fully parallel digital implementation of connectionist associative memory

Kyusun Choi, William S. Adams

Computer Science and Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm ² CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.

Original language	English (US)
Article number	5727297
Pages (from-to)	6.6.1-6.6.4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1992.591144
State	Published - 1992
Event	14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, United States Duration: May 3 1992 → May 6 1992

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/CICC.1992.591144

Cite this

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title = "Fully parallel digital implementation of connectionist associative memory",

abstract = "In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.",

author = "Kyusun Choi and Adams, {William S.}",

year = "1992",

doi = "10.1109/CICC.1992.591144",

language = "English (US)",

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AU - Choi, Kyusun

AU - Adams, William S.

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N2 - In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.

AB - In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.

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U2 - 10.1109/CICC.1992.591144

DO - 10.1109/CICC.1992.591144

M3 - Conference article

AN - SCOPUS:84870003984

SN - 0886-5930

SP - 6.6.1-6.6.4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 5727297

T2 - 14th Annual Custom Integrated Circuits Conference, CICC 1992

Y2 - 3 May 1992 through 6 May 1992

ER -

Fully parallel digital implementation of connectionist associative memory

Abstract

All Science Journal Classification (ASJC) codes

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