Fully self-aligned tri-layer a-Si: H TFT with ultra-thin active layer

Parasitic capacitance from gate-to-source contact overlap is a major factor limiting the performance of hydrogenated amorphous silicon thin-film transistors for active matrix liquid crystal displays. A self-aligned thin-film transistors is proposed to minimize this parasitic capacitance. Self-alignment is typically achieved with a single backside exposure photolithography step, using the bottom gate to define the channel region. A simple processing method is described for fully self-aligned tri-layer thin-film transistor (TFT) with deposited n⁺ contacts. In addition, these fully self-aligned TFTs have an ultra-thin a-Si:H layer that results in improved performance.