TY - GEN
T1 - GemDroid
T2 - 2014 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2014
AU - Nachiappan, Nachiappan Chidambaram
AU - Yedlapalli, Praveen
AU - Soundararajan, Niranjan
AU - Kandemir, Mahmut T.
AU - Sivasubramaniam, Anand
AU - Das, Chita R.
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014
Y1 - 2014
N2 - As the demand for feature-rich mobile systems such as smart-phones and tablets has outpaced other computing systems and is expected to continue at a faster rate, it is projected that SoCs with tens of cores and hundreds of IPs (or ac-celerator) will be designed to provide unprecedented level of features and functionality in future. Design of such mo-bile systems with required QoS and power budgets along with other design constraints will be a daunting task for computer architects since any ad hoc, piece-meal solution is unlikely to result in an optimal design. This requires early exploration of the complete design space to understand the system-level design trade-offs. To the best of our knowledge, there is no such publicly available tool to conduct a holistic evaluation of mobile platforms consisting of cores, IPs and system software. This paper presents GemDroid, a comprehensive simula-tion infrastructure to address these concerns. GemDroid has been designed by integrating the Android open-source em-ulator for facilitating execution of mobile applications, the GEM5 core simulator for analyzing the CPU and memory centric designs, and models for several IPs to collectively study their impact on system-level performance and power. Analyzing a spectrum of applications with GemDroid, we observed that the memory subsystem is a vital cog in the mobile platform because, it needs to handle both core and IP traffic, which have very different characteristics. Con-sequently, we present a heterogeneous memory controller (HMC) design, where we divide the memory physically into two address regions, where the first region with one memory controller (MC) handles core-specific application data and the second region with another MC handles all IP related data. The proposed modifications to the memory controller design results in an average 25% reduction in execution time for CPU bound applications, up to 11% reduction in frame drops, and on average 17% reduction in CPU busy time for on-screen (IP bound) applications..
AB - As the demand for feature-rich mobile systems such as smart-phones and tablets has outpaced other computing systems and is expected to continue at a faster rate, it is projected that SoCs with tens of cores and hundreds of IPs (or ac-celerator) will be designed to provide unprecedented level of features and functionality in future. Design of such mo-bile systems with required QoS and power budgets along with other design constraints will be a daunting task for computer architects since any ad hoc, piece-meal solution is unlikely to result in an optimal design. This requires early exploration of the complete design space to understand the system-level design trade-offs. To the best of our knowledge, there is no such publicly available tool to conduct a holistic evaluation of mobile platforms consisting of cores, IPs and system software. This paper presents GemDroid, a comprehensive simula-tion infrastructure to address these concerns. GemDroid has been designed by integrating the Android open-source em-ulator for facilitating execution of mobile applications, the GEM5 core simulator for analyzing the CPU and memory centric designs, and models for several IPs to collectively study their impact on system-level performance and power. Analyzing a spectrum of applications with GemDroid, we observed that the memory subsystem is a vital cog in the mobile platform because, it needs to handle both core and IP traffic, which have very different characteristics. Con-sequently, we present a heterogeneous memory controller (HMC) design, where we divide the memory physically into two address regions, where the first region with one memory controller (MC) handles core-specific application data and the second region with another MC handles all IP related data. The proposed modifications to the memory controller design results in an average 25% reduction in execution time for CPU bound applications, up to 11% reduction in frame drops, and on average 17% reduction in CPU busy time for on-screen (IP bound) applications..
UR - http://www.scopus.com/inward/record.url?scp=84904289727&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84904289727&partnerID=8YFLogxK
U2 - 10.1145/2591971.2591973
DO - 10.1145/2591971.2591973
M3 - Conference contribution
AN - SCOPUS:84904289727
SN - 9781450327893
T3 - SIGMETRICS 2014 - Proceedings of the 2014 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems
SP - 355
EP - 366
BT - SIGMETRICS 2014 - Proceedings of the 2014 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems
PB - Association for Computing Machinery
Y2 - 16 June 2014 through 20 June 2014
ER -