Glass Panel Packaging, as the Most Leading-Edge Packaging: Technologies and Applications

Rao Tummala, Bartlet Deprospo, Shreya Dwarakanath, Siddharth Ravichandran, Pratik Nimbalkar, Nithin Nedumthakady, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

The semiconductor and systems landscape are changing dramatically. As Moore's law begins to come to an end for many reasons that include minimal increase in transistor performance and in computer performance from node to node but at higher power, the industry has begun to shift to interconnections, referred to as Moore's law for Packaging. This focus addresses both the need for homogeneous and heterogeneous integrations by interconnecting smaller chips and smaller components with higher performance at lower cost and interconnecting them as multichip in 2.5 and 3D architectures. This is also called extending Moore's law, not in a single chip but with multiple chips interconnected horizontally and vertically. This strategy is very consistent with the dramatic and emerging changes in electronic systems such as in HPC, AI and a new era of self-driving and electric cars that potentially think and drive better than humans. This requires device, packaging, and computing architecture paradigms with an entirely different vision and strategy than transistor scaling alone. Packaging, which can be viewed broadly as system scaling, is now viewed as replacing Moore's law for enabling better devices and better systems, unlike in the past. Glass packaging is being developed by Georgia Tech and its industry partners, as the most leading-edge packaging, consistent with the above systems needs in cost, performance, functionality, reliability, and miniaturization. This paper describes the critical glass packaging technologies, their RD and commercialization status as well as all the current and future applications. It compares and contrasts glass packaging against other leading-edge technologies such as Si and embedded packaging.

Original languageEnglish (US)
Title of host publication2020 Pan Pacific Microelectronics Symposium, Pan Pacific 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781944543143
DOIs
StatePublished - Feb 2020
Event2020 Pan Pacific Microelectronics Symposium, Pan Pacific 2020 - Kohala Coast, United States
Duration: Feb 10 2020Feb 13 2020

Publication series

Name2020 Pan Pacific Microelectronics Symposium, Pan Pacific 2020

Conference

Conference2020 Pan Pacific Microelectronics Symposium, Pan Pacific 2020
Country/TerritoryUnited States
CityKohala Coast
Period2/10/202/13/20

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering
  • Mechanics of Materials
  • Safety, Risk, Reliability and Quality

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