Global register alias table: Boosting sequential program on multi-core

Jianliang Ma, Chunhao Wang, Baozhong Yu, Tianzhou Chen

Research output: Contribution to journalArticlepeer-review


Executing sequential program on multi-core is crucial for accommodating Instruction Level Parallelism (ILP) in Chip Multi-Processor (CMP) architecture. One widely used method for steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings about much hardware complexity and die area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate sequential program execution across cores. The GRAT drastically reduces the area overhead and design complexity of steering instructions without introducing additional programming effort or compiler support. Dynamic reconfiguration is also implemented to support efficient parallel program execution. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent work which requires a complex steering unit.

Original languageEnglish (US)
Pages (from-to)957-964
Number of pages8
JournalFuture Generation Computer Systems
Issue number6
StatePublished - Jun 2012

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications


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