The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for Cutting down access times and lowering miss rates. However, it was only recently that the first exploration on prefetching TLB entries ahead of their need was undertaken and a mechanism called Recency Prefetching was proposed. There is a large body of literature on prefetching for caches, and it is not clear how they can be adapted (or if the issues are different) for TLBs, how well suited they are for TLB prefetching, and how they compare with the recency pre fetching mechanism. This paper presents the first detailed comparison of different prefetching mechanisms (previously proposed for caches) - arbitrary stride prefetching, and markov prefetching - for TLB entries, and evaluates their pros and cons. In addition, this paper proposes a novel prefetching mechanism, called Distance Prefetching, that attempts to capture patterns in the reference behavior in a smaller space than earlier proposals. Using detailed simulations of a wide variety of applications (56 in all) from different benchmark suites and all the SPEC CPU2000 applications, this paper demonstrates the benefits of distance prefetching.
|Number of pages
|Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
|Published - Jan 1 2002
|29th Annual International Symposium on Computer Architecture - Anchorage, AK, United States
Duration: May 25 2002 → May 29 2002
All Science Journal Classification (ASJC) codes
- Hardware and Architecture