HeTERO: Hybrid topology exploration for RF-based on-chip networks

Soumya Eachempati; Reetuparna Das; Vijaykrishnan Narayanan; Yuan Xie; Suman Datta; Chita R. Das

HeTERO: Hybrid topology exploration for RF-based on-chip networks

Soumya Eachempati, Reetuparna Das, Vijaykrishnan Narayanan, Yuan Xie, Suman Datta, Chita R. Das

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

Future microprocessors are predicted to consist of 10s to 100s of cores running several concurrent tasks. A scalable communication fabric is required to connect these components and thus, giving birth to networks on silicon, also known as Network-on-Chip (NoC). NoCs are being used as the de facto solution for integrating the multicore architectures, as opposed to point-topoint global wiring, shared buses, or monolithic crossbars, because of their scalability and predictable electrical properties.

Original language	English (US)
Title of host publication	Communication Architectures for Systems-on-Chip
Publisher	CRC Press
Pages	201-248
Number of pages	48
ISBN (Electronic)	9781439841716
ISBN (Print)	9781138117945
State	Published - Jan 1 2011

All Science Journal Classification (ASJC) codes

General Computer Science

Cite this

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abstract = "Future microprocessors are predicted to consist of 10s to 100s of cores running several concurrent tasks. A scalable communication fabric is required to connect these components and thus, giving birth to networks on silicon, also known as Network-on-Chip (NoC). NoCs are being used as the de facto solution for integrating the multicore architectures, as opposed to point-topoint global wiring, shared buses, or monolithic crossbars, because of their scalability and predictable electrical properties.",

author = "Soumya Eachempati and Reetuparna Das and Vijaykrishnan Narayanan and Yuan Xie and Suman Datta and Das, \{Chita R.\}",

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AU - Eachempati, Soumya

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AU - Narayanan, Vijaykrishnan

AU - Xie, Yuan

AU - Datta, Suman

AU - Das, Chita R.

PY - 2011/1/1

Y1 - 2011/1/1

N2 - Future microprocessors are predicted to consist of 10s to 100s of cores running several concurrent tasks. A scalable communication fabric is required to connect these components and thus, giving birth to networks on silicon, also known as Network-on-Chip (NoC). NoCs are being used as the de facto solution for integrating the multicore architectures, as opposed to point-topoint global wiring, shared buses, or monolithic crossbars, because of their scalability and predictable electrical properties.

AB - Future microprocessors are predicted to consist of 10s to 100s of cores running several concurrent tasks. A scalable communication fabric is required to connect these components and thus, giving birth to networks on silicon, also known as Network-on-Chip (NoC). NoCs are being used as the de facto solution for integrating the multicore architectures, as opposed to point-topoint global wiring, shared buses, or monolithic crossbars, because of their scalability and predictable electrical properties.

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M3 - Chapter

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BT - Communication Architectures for Systems-on-Chip

PB - CRC Press

ER -

HeTERO: Hybrid topology exploration for RF-based on-chip networks

Abstract

All Science Journal Classification (ASJC) codes

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