High density group iv semiconductor nanowire arrays fabricated in nanoporous alumina templates

Joan M. Redwing, Sarah M. Dilts, Kok Keong Lew, Alexana Cranmer, Suzanne E. Mohney

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations


The fabrication of high density arrays of semiconductor nanowires is of interest for nanoscale electronics, chemical and biological sensing and energy conversion applications. We have investigated the synthesis, intentional doping and electrical characterization of Si and Ge nanowires grown by the vapor-liquid-solid (VLS) method in nanoporous alumina membranes. Nanoporous membranes provide a convenient platform for nanowire growth and processing, enabling control of wire diameter via pore size and the integration of contact metals for electrical testing. For VLS growth in nanoporous materials, reduced pressures and temperatures are required in order to promote the diffusion of reactants into the pore without premature decomposition on the membrane surface or pore walls. The effect of growth conditions on the growth rate of Si and Ge nanowires from SiH 4 and GeH 4 sources, respectively, was investigated and compared. In both cases, the measured activation energies for nanowire growth were substantially lower than activation energies typically reported for Si and Ge thin film deposition under similar growth conditions, suggesting that gold plays a catalytic role in the VLS growth process. Intentionally doped SiNW arrays were also prepared using trimethylboron (TMB) and phosphine (PH 3) as p-type and n-type dopant sources, respectively. Nanowire resistivities were calculated from plots of the array resistance as a function of nanowire length. A decrease in resistivity was observed for both n-type and p-type doped SiNW arrays compared to those grown without the addition of a dopant source.

Original languageEnglish (US)
Article number60030S
JournalProceedings of SPIE - The International Society for Optical Engineering
StatePublished - 2005
EventNanostructure Integration Techniques for Manufacturable Devices, Circuits, and Systems: Interfaces, Interconnects, and Nanosystems - Boston, MA, United States
Duration: Oct 23 2005Oct 25 2005

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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