TY - GEN
T1 - High density packaging in 2010 and beyond
AU - Tummala, R. R.
AU - Sundaram, V.
AU - Liu, Fuhan
AU - White, G.
AU - Hattacharya, S.
AU - Pulugurtha, R. M.
AU - Swaminathan, M.
AU - Dalmia, S.
AU - Laskar, J.
AU - Jokerst, N. M.
AU - Chow, Sang Yeon
N1 - Funding Information:
The authors wish to thank the National Science Foundation (grant number EEC-9402723), its industry partners for their support, and all PRC faculty, students and research staff for their contributions to this work.
Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2003 with 100 nm features, pitch of area array I/Os of the nano ICs will move towards 20-100 micron. Increasing system functionality and system-on-a-chip will place demands on the package to support extremely high digital clock speeds beyond 5 GHz, RF signals to 40 GHz, and optical data rates beyond 100 Gbps all on a single, highly integrated package or board. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends both in IC and systems packaging including SIP, wafer level packaging are steps in the right direction, but represent partial system solutions. The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board. This paper reviews systems, IC, and high density packaging trends and summarizes the latest PRC developments in high density SOP packaging technology.
AB - As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2003 with 100 nm features, pitch of area array I/Os of the nano ICs will move towards 20-100 micron. Increasing system functionality and system-on-a-chip will place demands on the package to support extremely high digital clock speeds beyond 5 GHz, RF signals to 40 GHz, and optical data rates beyond 100 Gbps all on a single, highly integrated package or board. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends both in IC and systems packaging including SIP, wafer level packaging are steps in the right direction, but represent partial system solutions. The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board. This paper reviews systems, IC, and high density packaging trends and summarizes the latest PRC developments in high density SOP packaging technology.
UR - http://www.scopus.com/inward/record.url?scp=84966480068&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84966480068&partnerID=8YFLogxK
U2 - 10.1109/EMAP.2002.1188809
DO - 10.1109/EMAP.2002.1188809
M3 - Conference contribution
AN - SCOPUS:84966480068
T3 - Proceedings of the 4th International Symposium on Electronic Materials and Packaging, EMAP 2002
SP - 30
EP - 36
BT - Proceedings of the 4th International Symposium on Electronic Materials and Packaging, EMAP 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th International Symposium on Electronic Materials and Packaging, EMAP 2002
Y2 - 4 December 2002 through 6 December 2002
ER -