TY - GEN
T1 - High performance array processor for video decoding
AU - Lee, J.
AU - Vijaykrishnan, N.
AU - Irwin, M. J.
PY - 2005
Y1 - 2005
N2 - In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 μm CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.
AB - In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 μm CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.
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M3 - Conference contribution
AN - SCOPUS:26844520793
SN - 076952365X
SN - 9780769523651
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
SP - 28
EP - 33
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
A2 - Smailagic, A.
A2 - Ranganathan, N.
T2 - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Y2 - 11 May 2005 through 12 May 2005
ER -