High-speed, low-voltage complementary heterostructure FET circuit technology

  • R. A. Kiehl
  • , J. Yates
  • , L. F. Palmateer
  • , S. L. Wright
  • , D. J. Frank
  • , T. N. Jackson
  • , J. F. Degelormo
  • , A. J. Fleischman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.

Original languageEnglish (US)
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
PublisherPubl by IEEE
Pages101-104
Number of pages4
ISBN (Print)078030196X
StatePublished - Jan 1992
Event13th Annual GaAs IC Symposium Technical Digest - Monterey, CA, USA
Duration: Oct 20 1991Oct 23 1991

Publication series

NameTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Other

Other13th Annual GaAs IC Symposium Technical Digest
CityMonterey, CA, USA
Period10/20/9110/23/91

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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