High-speed protocol parallel implementation: Design and analysis

Thomas F. La Porta, M. Schwartz

Research output: Chapter in Book/Report/Conference proceedingChapter

5 Scopus citations


This paper presents a multiprocessor architecture for the parallel implementation of the MultiStream Protocol, MSP, a new feature-rich transport protocol. The parallelism of the protocol implementation is based on protocol functions such as error correction, error notification, etc. By dividing the processing based on protocol functionality, the architecture not only achieves high throughput, but reduces the end-to-end processing latency of the protocol as well. In addition, the variation, or jitter, in the interpacket arrival times at the protocol receiver is stabilized. Analysis of a software implementation of MSP using the architecture presented in this paper demonstrates that if 10-MIPS processors are used to implement the protocol along with practical hardware support, the architecture may support over 1 Gbps of throughput at the transport layer.

Original languageEnglish (US)
Title of host publicationIFIP Transactions C
Subtitle of host publicationCommunication Systems
EditorsA. Danthine, O. Spaniol
PublisherPubl by Elsevier Science Publishers B.V.
Number of pages16
ISBN (Print)0444814817
StatePublished - Dec 1 1993
EventProceedings of the IFIP TC6/WG6.4 4th International Conference on High Performance Networking - Liege, Belg
Duration: Dec 14 1992Dec 18 1992


OtherProceedings of the IFIP TC6/WG6.4 4th International Conference on High Performance Networking
CityLiege, Belg

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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