High-speed protocol parallel implementation: Design and analysis

Thomas F. La Porta; M. Schwartz

High-speed protocol parallel implementation: Design and analysis

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This paper presents a multiprocessor architecture for the parallel implementation of the MultiStream Protocol, MSP, a new feature-rich transport protocol. The parallelism of the protocol implementation is based on protocol functions such as error correction, error notification, etc. By dividing the processing based on protocol functionality, the architecture not only achieves high throughput, but reduces the end-to-end processing latency of the protocol as well. In addition, the variation, or jitter, in the interpacket arrival times at the protocol receiver is stabilized. Analysis of a software implementation of MSP using the architecture presented in this paper demonstrates that if 10-MIPS processors are used to implement the protocol along with practical hardware support, the architecture may support over 1 Gbps of throughput at the transport layer.

Original language	English (US)
Title of host publication	IFIP Transactions C
Subtitle of host publication	Communication Systems
Editors	A. Danthine, O. Spaniol
Publisher	Publ by Elsevier Science Publishers B.V.
Pages	135-150
Number of pages	16
Edition	C-14
ISBN (Print)	0444814817
State	Published - Dec 1 1993
Event	Proceedings of the IFIP TC6/WG6.4 4th International Conference on High Performance Networking - Liege, Belg Duration: Dec 14 1992 → Dec 18 1992

Other

Other	Proceedings of the IFIP TC6/WG6.4 4th International Conference on High Performance Networking
City	Liege, Belg
Period	12/14/92 → 12/18/92

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

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title = "High-speed protocol parallel implementation: Design and analysis",

abstract = "This paper presents a multiprocessor architecture for the parallel implementation of the MultiStream Protocol, MSP, a new feature-rich transport protocol. The parallelism of the protocol implementation is based on protocol functions such as error correction, error notification, etc. By dividing the processing based on protocol functionality, the architecture not only achieves high throughput, but reduces the end-to-end processing latency of the protocol as well. In addition, the variation, or jitter, in the interpacket arrival times at the protocol receiver is stabilized. Analysis of a software implementation of MSP using the architecture presented in this paper demonstrates that if 10-MIPS processors are used to implement the protocol along with practical hardware support, the architecture may support over 1 Gbps of throughput at the transport layer.",

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AU - Schwartz, M.

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AB - This paper presents a multiprocessor architecture for the parallel implementation of the MultiStream Protocol, MSP, a new feature-rich transport protocol. The parallelism of the protocol implementation is based on protocol functions such as error correction, error notification, etc. By dividing the processing based on protocol functionality, the architecture not only achieves high throughput, but reduces the end-to-end processing latency of the protocol as well. In addition, the variation, or jitter, in the interpacket arrival times at the protocol receiver is stabilized. Analysis of a software implementation of MSP using the architecture presented in this paper demonstrates that if 10-MIPS processors are used to implement the protocol along with practical hardware support, the architecture may support over 1 Gbps of throughput at the transport layer.

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Y2 - 14 December 1992 through 18 December 1992

ER -

High-speed protocol parallel implementation: Design and analysis

Abstract

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All Science Journal Classification (ASJC) codes

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