TY - GEN
T1 - High-speed simulation for neuron system base on FPGA
AU - Zhang, Ronghua
AU - Wang, Jiang
AU - Li, Shuangshuang
AU - Che, Yanqiu
PY - 2010
Y1 - 2010
N2 - Method for neuromorphic hardware implementing base on FPGA is researched. The concept of pipeline operator and pipeline model, which can supply a mathematical deduction for realizing the single-core multi-model, is defined. A realization of Morris-Lecar neural model with 12 stages pipeline is accomplished, and the code is embedded into the "Digital Neuromorphic Hardware Platform". Error analysis for the result has been done in this paper.
AB - Method for neuromorphic hardware implementing base on FPGA is researched. The concept of pipeline operator and pipeline model, which can supply a mathematical deduction for realizing the single-core multi-model, is defined. A realization of Morris-Lecar neural model with 12 stages pipeline is accomplished, and the code is embedded into the "Digital Neuromorphic Hardware Platform". Error analysis for the result has been done in this paper.
UR - http://www.scopus.com/inward/record.url?scp=78650254105&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650254105&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:78650254105
SN - 9787894631046
T3 - Proceedings of the 29th Chinese Control Conference, CCC'10
SP - 5500
EP - 5504
BT - Proceedings of the 29th Chinese Control Conference, CCC'10
T2 - 29th Chinese Control Conference, CCC'10
Y2 - 29 July 2010 through 31 July 2010
ER -