High-throughput and low-power DSP using clocked-CMOS circuitry

We argue that the clocked-CMOS (C²MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market of portable electronics. By the virtue of self latching gates allowing very fine-grained pipelining, avoidance of precharge and short circuit power consumption, the C²MOS circuit offers very good power-delay efficiency. We support our claims through the design of an 8-bit unsigned binary multiplier with pipelining at the gate level which can produce 500 million multiplications per second consuming only 0.8 W power using 1.0 micron technology and 3.3 V power supply. By comparison the fastest previously existing pipelined multiplier has a throughput rate of 400 million multiplications per second consuming 0.8 W power at 0.8 micron technology, 5 V, using wave-pipelining.