Hybrid-comp: A criticality-aware compressed last-level cache

Amin Jadidi, Mohammad Arjomand, Mahmut T. Kandemir, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


Cache compression is a promising technique to increase on-chip cache capacity and to decrease off-chip bandwidth usage. While prior compression techniques always consider a trade-off between compression ratio and decompression latency, they are oblivious to the variation in criticality of different cache blocks. In multi-core processors, last-level cache (LLC) is logically shared but physically distributed among cores. In this work, we demonstrate that, cache blocks within such nonuniform architecture exhibit different sensitivity to the access latency. Owing to this behavior, we propose a criticality-aware compressed LLC that favors lower latency over higher capacity based on the criticality of the data blocks. Based on our studies on a 16-core processor with 4MB LLC, our proposed criticality-aware mechanism improves the system performance comparable to that of with an 8MB uncompressed LLC.

Original languageEnglish (US)
Title of host publication2018 19th International Symposium on Quality Electronic Design, ISQED 2018
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781538612149
StatePublished - May 9 2018
Event19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States
Duration: Mar 13 2018Mar 14 2018

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295


Other19th International Symposium on Quality Electronic Design, ISQED 2018
Country/TerritoryUnited States
CitySanta Clara

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality


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