TY - GEN
T1 - Hybrid technique for mass synthesis of field effect transistors using gallium nitride nanowires
AU - Nguyen, Son
AU - Delalic, Joan Zdenka
AU - Catchmark, Jeffrey M.
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2005
Y1 - 2005
N2 - To date, there have been many researches on the characteristics, the control of the size and location of gallium nitride nanowires (GaN NWs); however, mass production of electronic devices is still being studied. This paper proposes a hybrid method to fabricate arrays of n-type Field Effect Transistors (FET) using GaN NWs. The fabrication process involves both top-down and bottom-up techniques. The former will be used to obtain the gates and metal contacts in the transistors, and to determine the desired locations of catalytic particles (gold) needed for chemical reaction to grow NWs. The latter will help in the development of a uniform channel (with desired diameter and characteristic) between the source and the drain terminals. The success of the research will eliminate the problem of "pick and place" in the fabrication process. Ultimately, this will lead to high volume manufacturing of building blocks for integrated circuits.
AB - To date, there have been many researches on the characteristics, the control of the size and location of gallium nitride nanowires (GaN NWs); however, mass production of electronic devices is still being studied. This paper proposes a hybrid method to fabricate arrays of n-type Field Effect Transistors (FET) using GaN NWs. The fabrication process involves both top-down and bottom-up techniques. The former will be used to obtain the gates and metal contacts in the transistors, and to determine the desired locations of catalytic particles (gold) needed for chemical reaction to grow NWs. The latter will help in the development of a uniform channel (with desired diameter and characteristic) between the source and the drain terminals. The success of the research will eliminate the problem of "pick and place" in the fabrication process. Ultimately, this will lead to high volume manufacturing of building blocks for integrated circuits.
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M3 - Conference contribution
AN - SCOPUS:84876908423
SN - 0930815777
SN - 9780930815776
T3 - Proceedings - 2005 International Symposium on Microelectronics, IMAPS 2005
SP - 238
EP - 243
BT - Proceedings - 2005 International Symposium on Microelectronics, IMAPS 2005
T2 - 38th International Symposium on Microelectronics, IMAPS 2005
Y2 - 25 September 2005 through 29 September 2005
ER -