Abstract
Processor caches already play a critical role in the performance of today's computer systems. At the same time, the data integrity of words coming out of the caches can have serious consequences on the ability of a program to execute correctly, or even to proceed. The integrity checks need to be performed in a time-sensitive manner to not slow down the execution when there are no errors as in the common case, and should not excessively increase the power budget of the caches which is already high. ECC and parity-based protection techniques in use today fall at either extremes in terms of compromising one criteria for another, i.e., reliability for performance or vice-versa. This paper proposes a novel solution to this problem by allowing in-cache replication, wherein reliability can be enhanced without excessively slowing down cache accesses or requiring significant area cost increases. The mechanism is fairly power efficient in comparison to other alternatives as well. In particular, the solution replicates data that is in active use within the cache itself while evicting those that may not be needed in the near future. Our experiments show that a large fraction of the data read from the cache have replicas available with this optimization.
Original language | English (US) |
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Pages | 291-300 |
Number of pages | 10 |
State | Published - 2003 |
Event | 2003 International Conference on Dependable Systems and Networks - San Francisco, CA, United States Duration: Jun 22 2003 → Jun 25 2003 |
Other
Other | 2003 International Conference on Dependable Systems and Networks |
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Country/Territory | United States |
City | San Francisco, CA |
Period | 6/22/03 → 6/25/03 |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Networks and Communications