TY - GEN
T1 - IMACE
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
AU - Nagarajan, Karthikeyan
AU - Ensan, Sina Sayyah
AU - Mandal, Swagata
AU - Ghosh, Swaroop
AU - Chattopadhyay, Anupam
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.
AB - Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.
UR - http://www.scopus.com/inward/record.url?scp=85072968779&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85072968779&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2019.00098
DO - 10.1109/ISVLSI.2019.00098
M3 - Conference contribution
AN - SCOPUS:85072968779
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 513
EP - 518
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
Y2 - 15 July 2019 through 17 July 2019
ER -
