IMACE: In-Memory Acceleration of Classic McEliece Encoder

Karthikeyan Nagarajan; Sina Sayyah Ensan; Swagata Mandal; Swaroop Ghosh; Anupam Chattopadhyay

doi:10.1109/ISVLSI.2019.00098

IMACE: In-Memory Acceleration of Classic McEliece Encoder

Karthikeyan Nagarajan
, Sina Sayyah Ensan
, Swagata Mandal
, Swaroop Ghosh
, Anupam Chattopadhyay

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.

Original language	English (US)
Title of host publication	Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Publisher	IEEE Computer Society
Pages	513-518
Number of pages	6
ISBN (Electronic)	9781538670996
DOIs	https://doi.org/10.1109/ISVLSI.2019.00098
State	Published - Jul 2019
Event	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States Duration: Jul 15 2019 → Jul 17 2019

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2019-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Country/Territory	United States
City	Miami
Period	7/15/19 → 7/17/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2019.00098

Cite this

Nagarajan, K., Ensan, S. S., Mandal, S., Ghosh, S., & Chattopadhyay, A. (2019). IMACE: In-Memory Acceleration of Classic McEliece Encoder. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 513-518). Article 8839477 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2019.00098

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title = "IMACE: In-Memory Acceleration of Classic McEliece Encoder",

abstract = "Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46\%-97\% reduction in energy consumption compared to the FPGA-based implementation.",

author = "Karthikeyan Nagarajan and Ensan, \{Sina Sayyah\} and Swagata Mandal and Swaroop Ghosh and Anupam Chattopadhyay",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 ; Conference date: 15-07-2019 Through 17-07-2019",

year = "2019",

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doi = "10.1109/ISVLSI.2019.00098",

language = "English (US)",

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Nagarajan, K, Ensan, SS, Mandal, S, Ghosh, S & Chattopadhyay, A 2019, IMACE: In-Memory Acceleration of Classic McEliece Encoder. in Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019., 8839477, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2019-July, IEEE Computer Society, pp. 513-518, 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, United States, 7/15/19. https://doi.org/10.1109/ISVLSI.2019.00098

IMACE: In-Memory Acceleration of Classic McEliece Encoder. / Nagarajan, Karthikeyan; Ensan, Sina Sayyah; Mandal, Swagata et al.
Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, 2019. p. 513-518 8839477 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Nagarajan, Karthikeyan

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N2 - Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.

AB - Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.

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M3 - Conference contribution

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Y2 - 15 July 2019 through 17 July 2019

ER -

IMACE: In-Memory Acceleration of Classic McEliece Encoder

Abstract

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UN SDGs

All Science Journal Classification (ASJC) codes

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