Impact of circuit degradation on FPGA design security

Han Wei Chen; Suresh Srinivasan; Yuan Xie; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2011.81

Impact of circuit degradation on FPGA design security

Han Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.

Original language	English (US)
Title of host publication	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages	230-235
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2011.81
State	Published - 2011
Event	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India Duration: Jul 4 2011 → Jul 6 2011

Publication series

Name	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Other

Other	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Country/Territory	India
City	Chennai
Period	7/4/11 → 7/6/11

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2011.81

Cite this

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title = "Impact of circuit degradation on FPGA design security",

abstract = "SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.",

author = "Chen, {Han Wei} and Suresh Srinivasan and Yuan Xie and Vijaykrishnan Narayanan",

year = "2011",

doi = "10.1109/ISVLSI.2011.81",

language = "English (US)",

isbn = "9780769544472",

series = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

pages = "230--235",

booktitle = "Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011",

note = "2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 ; Conference date: 04-07-2011 Through 06-07-2011",

}

Chen, HW, Srinivasan, S, Xie, Y & Narayanan, V 2011, Impact of circuit degradation on FPGA design security. in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011., 5992485, Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, pp. 230-235, 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, India, 7/4/11. https://doi.org/10.1109/ISVLSI.2011.81

Impact of circuit degradation on FPGA design security. / Chen, Han Wei; Srinivasan, Suresh; Xie, Yuan et al.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. 2011. p. 230-235 5992485 (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Impact of circuit degradation on FPGA design security

AU - Chen, Han Wei

AU - Srinivasan, Suresh

AU - Xie, Yuan

AU - Narayanan, Vijaykrishnan

PY - 2011

Y1 - 2011

N2 - SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.

AB - SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.

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BT - Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

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Impact of circuit degradation on FPGA design security

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All Science Journal Classification (ASJC) codes

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