@inproceedings{3044ecf71cf24e4ab896bddab0b2a9ff,
title = "Impact of contact and local interconnect scaling on logic performance",
abstract = "We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.",
author = "S. Datta and R. Pandey and A. Agrawal and Gupta, {S. K.} and R. Arghavani",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 34th Symposium on VLSI Technology, VLSIT 2014 ; Conference date: 09-06-2014 Through 12-06-2014",
year = "2014",
month = sep,
day = "8",
doi = "10.1109/VLSIT.2014.6894406",
language = "English (US)",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",
address = "United States",
}