Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors

Martin Saint-Laurent; Madhavan Swaminathan

Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors

Martin Saint-Laurent
, Madhavan Swaminathan

Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

This paper discusses the tradeoff between power and clock inaccuracy for high-frequency microprocessors. A new expression for the optimal tradeoff is used to analyze the impact of interconnects on the optimal design point for a simple clock distribution network. The result is that the impact is considerable and that the cost of deviating from the optimal structure is substantial.

Original language	English (US)
Pages	311-314
Number of pages	4
State	Published - 2000
Event	9th Topical Meeting on Electrical Performance of Electronic Packaging - Scottsdale, AZ, USA Duration: Oct 23 2000 → Oct 25 2000

Conference

Conference	9th Topical Meeting on Electrical Performance of Electronic Packaging
City	Scottsdale, AZ, USA
Period	10/23/00 → 10/25/00

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@conference{d5b444064d7b4f0caf20e629f34bc98c,

title = "Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors",

abstract = "This paper discusses the tradeoff between power and clock inaccuracy for high-frequency microprocessors. A new expression for the optimal tradeoff is used to analyze the impact of interconnects on the optimal design point for a simple clock distribution network. The result is that the impact is considerable and that the cost of deviating from the optimal structure is substantial.",

author = "Martin Saint-Laurent and Madhavan Swaminathan",

year = "2000",

language = "English (US)",

pages = "311--314",

note = "9th Topical Meeting on Electrical Performance of Electronic Packaging ; Conference date: 23-10-2000 Through 25-10-2000",

}

TY - CONF

T1 - Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors

AU - Saint-Laurent, Martin

AU - Swaminathan, Madhavan

PY - 2000

Y1 - 2000

N2 - This paper discusses the tradeoff between power and clock inaccuracy for high-frequency microprocessors. A new expression for the optimal tradeoff is used to analyze the impact of interconnects on the optimal design point for a simple clock distribution network. The result is that the impact is considerable and that the cost of deviating from the optimal structure is substantial.

AB - This paper discusses the tradeoff between power and clock inaccuracy for high-frequency microprocessors. A new expression for the optimal tradeoff is used to analyze the impact of interconnects on the optimal design point for a simple clock distribution network. The result is that the impact is considerable and that the cost of deviating from the optimal structure is substantial.

UR - https://www.scopus.com/pages/publications/0034516284

UR - https://www.scopus.com/pages/publications/0034516284#tab=citedBy

M3 - Paper

AN - SCOPUS:0034516284

SP - 311

EP - 314

T2 - 9th Topical Meeting on Electrical Performance of Electronic Packaging

Y2 - 23 October 2000 through 25 October 2000

ER -

Impact of interconnects on the optimal power-performance tradeoff for clock distribution in microprocessors

Abstract

Conference

All Science Journal Classification (ASJC) codes

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