Impact of power-supply noise on timing in high-frequency microprocessors

Martin Saint-Laurent; Madhavan Swaminathan

doi:10.1109/EPEP.2002.1057928

Impact of power-supply noise on timing in high-frequency microprocessors

Martin Saint-Laurent, Madhavan Swaminathan

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.

Original language	English (US)
Title of host publication	Electrical Performance of Electronic Packaging, EPEP 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	261-264
Number of pages	4
ISBN (Electronic)	0780374517
DOIs	https://doi.org/10.1109/EPEP.2002.1057928
State	Published - 2002
Event	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States Duration: Oct 21 2002 → Oct 23 2002

Publication series

Name	IEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume	2002-January

Conference

Conference	11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Country/Territory	United States
City	Monterey
Period	10/21/02 → 10/23/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EPEP.2002.1057928

Cite this

Saint-Laurent, M., & Swaminathan, M. (2002). Impact of power-supply noise on timing in high-frequency microprocessors. In Electrical Performance of Electronic Packaging, EPEP 2002 (pp. 261-264). Article 1057928 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEP.2002.1057928

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title = "Impact of power-supply noise on timing in high-frequency microprocessors",

abstract = "This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium{\textregistered}4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.",

author = "Martin Saint-Laurent and Madhavan Swaminathan",

note = "Publisher Copyright: {\textcopyright} 2012 IEEE.; 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 ; Conference date: 21-10-2002 Through 23-10-2002",

year = "2002",

doi = "10.1109/EPEP.2002.1057928",

language = "English (US)",

series = "IEEE Topical Meeting on Electrical Performance of Electronic Packaging",

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Saint-Laurent, M & Swaminathan, M 2002, Impact of power-supply noise on timing in high-frequency microprocessors. in Electrical Performance of Electronic Packaging, EPEP 2002., 1057928, IEEE Topical Meeting on Electrical Performance of Electronic Packaging, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 261-264, 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002, Monterey, United States, 10/21/02. https://doi.org/10.1109/EPEP.2002.1057928

Impact of power-supply noise on timing in high-frequency microprocessors. / Saint-Laurent, Martin; Swaminathan, Madhavan.
Electrical Performance of Electronic Packaging, EPEP 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 261-264 1057928 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.

AB - This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.

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ER -

Impact of power-supply noise on timing in high-frequency microprocessors

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