TY - GEN
T1 - Impact of power-supply noise on timing in high-frequency microprocessors
AU - Saint-Laurent, Martin
AU - Swaminathan, Madhavan
N1 - Publisher Copyright:
© 2012 IEEE.
PY - 2002
Y1 - 2002
N2 - This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.
AB - This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.
UR - http://www.scopus.com/inward/record.url?scp=84886699132&partnerID=8YFLogxK
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U2 - 10.1109/EPEP.2002.1057928
DO - 10.1109/EPEP.2002.1057928
M3 - Conference contribution
AN - SCOPUS:84886699132
T3 - IEEE Topical Meeting on Electrical Performance of Electronic Packaging
SP - 261
EP - 264
BT - Electrical Performance of Electronic Packaging, EPEP 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Y2 - 21 October 2002 through 23 October 2002
ER -