Impact of power-supply noise on timing in high-frequency microprocessors

Martin Saint-Laurent, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53-GHz Pentium®4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.

Original languageEnglish (US)
Title of host publicationElectrical Performance of Electronic Packaging, EPEP 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages261-264
Number of pages4
ISBN (Electronic)0780374517
DOIs
StatePublished - 2002
Event11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 - Monterey, United States
Duration: Oct 21 2002Oct 23 2002

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume2002-January

Conference

Conference11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002
Country/TerritoryUnited States
CityMonterey
Period10/21/0210/23/02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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