Impact of power-supply noise on timing in high-frequency microprocessors

Martin Saint-Laurent, Madhavan Swaminathan

Research output: Contribution to journalArticlepeer-review

143 Scopus citations


This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduce clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation.

Original languageEnglish (US)
Pages (from-to)135-144
Number of pages10
JournalIEEE Transactions on Advanced Packaging
Issue number1
StatePublished - Feb 2004

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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