Impact of process scaling on the efficacy of leakage reduction schemes

Yuh Fang Tsai; David Duarte; N. Vijaykrishnan; Mary Jane Irwin

Impact of process scaling on the efficacy of leakage reduction schemes

Yuh Fang Tsai, David Duarte, N. Vijaykrishnan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

Original language	English (US)
Title of host publication	2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	3-11
Number of pages	9
State	Published - 2004
Event	2004 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: May 17 2004 → May 20 2004

Publication series

Name	2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other	2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	5/17/04 → 5/20/04

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{fe20c972ab6f4892876408ab7a30c37c,

title = "Impact of process scaling on the efficacy of leakage reduction schemes",

abstract = "The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.",

author = "Tsai, {Yuh Fang} and David Duarte and N. Vijaykrishnan and Irwin, {Mary Jane}",

year = "2004",

language = "English (US)",

isbn = "0780385284",

series = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT",

pages = "3--11",

booktitle = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT",

note = "2004 International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 17-05-2004 Through 20-05-2004",

}

Tsai, YF, Duarte, D, Vijaykrishnan, N & Irwin, MJ 2004, Impact of process scaling on the efficacy of leakage reduction schemes. in 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004 International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 3-11, 2004 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 5/17/04.

Impact of process scaling on the efficacy of leakage reduction schemes. / Tsai, Yuh Fang; Duarte, David; Vijaykrishnan, N. et al.
2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. p. 3-11 (2004 International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Impact of process scaling on the efficacy of leakage reduction schemes

AU - Tsai, Yuh Fang

AU - Duarte, David

AU - Vijaykrishnan, N.

AU - Irwin, Mary Jane

PY - 2004

Y1 - 2004

N2 - The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

AB - The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

UR - http://www.scopus.com/inward/record.url?scp=4143094905&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4143094905&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:4143094905

SN - 0780385284

SN - 9780780385283

T3 - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

SP - 3

EP - 11

BT - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

T2 - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Y2 - 17 May 2004 through 20 May 2004

ER -

Impact of process scaling on the efficacy of leakage reduction schemes

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

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