TY - GEN
T1 - Impact of process-variations in STTRAM and adaptive boosting for robustness
AU - Motaman, Seyedhamidreza
AU - Ghosh, Swaroop
AU - Rathi, Nitin
N1 - Publisher Copyright:
© 2015 EDAA.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10% due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80% power improvement compared to boosting all bit-cells and 13% performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.
AB - Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10% due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80% power improvement compared to boosting all bit-cells and 13% performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.
UR - http://www.scopus.com/inward/record.url?scp=84945935019&partnerID=8YFLogxK
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U2 - 10.7873/date.2015.1018
DO - 10.7873/date.2015.1018
M3 - Conference contribution
AN - SCOPUS:84945935019
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1431
EP - 1436
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Y2 - 9 March 2015 through 13 March 2015
ER -