TY - GEN
T1 - Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures
AU - Eachempati, S.
AU - Vijaykrishnan, N.
AU - Nieuwoudt, Arthur
AU - Massoud, Yehia
PY - 2007
Y1 - 2007
N2 - As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alternative interconnect solutions for future process technologies. In this paper, we investigate the impact of statistical variations in interconnect properties on FPGA timing yield (TY) when bundles of single-walled carbon nanotubes (SWCNT) are used as interconnect in the FPGA routing fabric. The results indicate that SWCNT bundle-based interconnect (SWCNTBI) can provide a superior performance-yield trade-off over FPGAs implemented using traditional CuI in future process technologies.
AB - As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alternative interconnect solutions for future process technologies. In this paper, we investigate the impact of statistical variations in interconnect properties on FPGA timing yield (TY) when bundles of single-walled carbon nanotubes (SWCNT) are used as interconnect in the FPGA routing fabric. The results indicate that SWCNT bundle-based interconnect (SWCNTBI) can provide a superior performance-yield trade-off over FPGAs implemented using traditional CuI in future process technologies.
UR - http://www.scopus.com/inward/record.url?scp=36348999644&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=36348999644&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2007.56
DO - 10.1109/ISVLSI.2007.56
M3 - Conference contribution
AN - SCOPUS:36348999644
SN - 0769528961
SN - 9780769528960
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures
SP - 516
EP - 517
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Y2 - 9 March 2007 through 11 March 2007
ER -