TY - GEN
T1 - Impact of technology scaling and packaging on dynamic voltage scaling techniques
AU - Duarte, D.
AU - Narayanan, Vijaykrishnan
AU - Irwin, Mary Jane
AU - Tsai, Y. F.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.
AB - This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.
UR - http://www.scopus.com/inward/record.url?scp=1942515905&partnerID=8YFLogxK
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U2 - 10.1109/ASIC.2002.1158064
DO - 10.1109/ASIC.2002.1158064
M3 - Conference contribution
AN - SCOPUS:1942515905
T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SP - 244
EP - 248
BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
A2 - Chickanosky, John
A2 - Krishnamurthy, Ram K.
A2 - Mukund, P.R.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Y2 - 25 September 2002 through 28 September 2002
ER -