Impact of technology scaling and packaging on dynamic voltage scaling techniques

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin, Y. F. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages244-248
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/TerritoryUnited States
CityRochester
Period9/25/029/28/02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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