TY - GEN
T1 - Implementation of power transmission lines to field programmable gate array ICs for managing signal and power integrity
AU - Kim, Sang Kyu
AU - Telikepalli, Satyanarayana
AU - Park, Sung Joo
AU - Swaminathan, Madhavan
AU - Keezer, David
AU - Han, Youkeun
PY - 2013
Y1 - 2013
N2 - As the operating frequencies of electronic devices increase, power and signal integrity have become a major issue. Simultaneous switching noise (SSN) is a major problem that restricts the performance of high speed digital systems. SSN leads to voltage fluctuations during data transitions which can induce excessive noise. SSN is caused by parasitic inductance components in the power delivery network (PDN) that manifest themselves through via transitions, apertures on reference plane, split planes and even solid planes. A new method has been proposed to address this problem, which employs power transmission lines (PTL) that supply power to integrated circuits instead of using the conventional power/ground plane pairs. This along with current balancing can be used to manage return path discontinuities and power supply noise. Many of the published work in this area have proved that the PTL concept is able to reduce SSN and enhance power and signal integrity. Pseudo-balanced power transmission line (PB-PTL) concept has been shown to improve performance and reduce power consumption. However, this has only been applied to relatively simple test vehicles. In this paper, the PB-PTL scheme has been extended for driving multiple I/O drivers in field programmable gate array (FPGA) ICs. This paper discusses the theory, simulation and measurement results for this implementation.
AB - As the operating frequencies of electronic devices increase, power and signal integrity have become a major issue. Simultaneous switching noise (SSN) is a major problem that restricts the performance of high speed digital systems. SSN leads to voltage fluctuations during data transitions which can induce excessive noise. SSN is caused by parasitic inductance components in the power delivery network (PDN) that manifest themselves through via transitions, apertures on reference plane, split planes and even solid planes. A new method has been proposed to address this problem, which employs power transmission lines (PTL) that supply power to integrated circuits instead of using the conventional power/ground plane pairs. This along with current balancing can be used to manage return path discontinuities and power supply noise. Many of the published work in this area have proved that the PTL concept is able to reduce SSN and enhance power and signal integrity. Pseudo-balanced power transmission line (PB-PTL) concept has been shown to improve performance and reduce power consumption. However, this has only been applied to relatively simple test vehicles. In this paper, the PB-PTL scheme has been extended for driving multiple I/O drivers in field programmable gate array (FPGA) ICs. This paper discusses the theory, simulation and measurement results for this implementation.
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U2 - 10.1109/ISEMC.2013.6670431
DO - 10.1109/ISEMC.2013.6670431
M3 - Conference contribution
AN - SCOPUS:84893158018
SN - 9781479904082
T3 - IEEE International Symposium on Electromagnetic Compatibility
SP - 322
EP - 327
BT - Proceedings - 2013 IEEE International Symposium on Electromagnetic Compatibility, EMC 2013
T2 - 2013 IEEE International Symposium on Electromagnetic Compatibility, EMC 2013
Y2 - 5 August 2013 through 9 August 2013
ER -