Implementation of Zero-Phase Zero Frequency Resonator Algorithm on FPGA

Epoch location is an important parameter for analysis of excitation source information from the speech signals. From several years lot of research have been done to find accurate locations of epochs. Epochs are instants at which vocal tract system are excited significantly. The prominent location of epochs can be found during the production of speech signals. However, due to the time varying nature of excitation source and the vocal tract system it is difficult to find accurate location of epochs. From various epoch extraction methods, Zero Frequency Filtering (ZFF) is the simplest and most widely used method to find accurate locations of epochs due to its highest identification rate and lowest false alarm rate among other algorithms. ZFF uses Infinite Impulse Response (IIR) filter followed by trend removal blocks however, the filter used in ZFF method is unstable which makes it unsuitable for practical implementation. In the literature many stable implementations of ZFF algorithms have been proposed. Compared to other stable algorithms of ZFF, Zero-phase Zero Frequency Resonator has simple design and gives the highest identification rate among other epoch extraction algorithms including ZFF. In this paper, the implementation of ZFF and ZP-ZFR has been proposed on FPGA board using Verilog which is Hardware Description Language (HDL).