TY - GEN
T1 - Implementing LDPC decoding on network-on-chip
AU - Theocharides, T.
AU - Link, G.
AU - Vijaykrishnan, N.
AU - Irwin, M. J.
PY - 2005
Y1 - 2005
N2 - Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to their ability to achieve near Shannon-limit communication channel capacity, the computational complexity of the decoder is a major concern. LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph. In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip communication fabric that provides a 1.2Gbps decoded throughput rate for a 3/4 code rate, 1024-bit block LDPC code. The proposed architecture can be reconfigured to support other LDPC codes of different block sizes and code rates. We also propose two novel power-aware optimizations that reduce the power consumption by up to 30%.
AB - Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to their ability to achieve near Shannon-limit communication channel capacity, the computational complexity of the decoder is a major concern. LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph. In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip communication fabric that provides a 1.2Gbps decoded throughput rate for a 3/4 code rate, 1024-bit block LDPC code. The proposed architecture can be reconfigured to support other LDPC codes of different block sizes and code rates. We also propose two novel power-aware optimizations that reduce the power consumption by up to 30%.
UR - http://www.scopus.com/inward/record.url?scp=27944498512&partnerID=8YFLogxK
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U2 - 10.1109/ICVD.2005.109
DO - 10.1109/ICVD.2005.109
M3 - Conference contribution
AN - SCOPUS:27944498512
SN - 0769522645
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 134
EP - 137
BT - Proceedings of the 18th International Conference on VLSI Design
T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Y2 - 3 January 2005 through 7 January 2005
ER -