TY - GEN
T1 - Improving bank-level parallelism for irregular applications
AU - Tang, Xulong
AU - Kandemir, Mahmut
AU - Yedlapalli, Praveen
AU - Kotra, Jagadish
N1 - Funding Information:
This research is supported in part by NSF grants #1213052, #1302557, #1409095, #1439021, #1439057, #1526750, #1629915 and #1629129, and a grant from Intel.
PY - 2016/12/14
Y1 - 2016/12/14
N2 - Observing that large multithreaded applications with irregular data access patterns exhibit very low memory bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve bank-level parallelism, and bank reuse is taken into account only if doing so does not hurt bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8% and an average execution time reduction of 18.3%.
AB - Observing that large multithreaded applications with irregular data access patterns exhibit very low memory bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve bank-level parallelism, and bank reuse is taken into account only if doing so does not hurt bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8% and an average execution time reduction of 18.3%.
UR - http://www.scopus.com/inward/record.url?scp=85009351778&partnerID=8YFLogxK
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U2 - 10.1109/MICRO.2016.7783760
DO - 10.1109/MICRO.2016.7783760
M3 - Conference contribution
AN - SCOPUS:85009351778
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
BT - MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture
PB - IEEE Computer Society
T2 - 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016
Y2 - 15 October 2016 through 19 October 2016
ER -