@inproceedings{da594e97d8684db2b475210639c6e5a2,
title = "Improving bank-level parallelism for irregular applications",
abstract = "Observing that large multithreaded applications with irregular data access patterns exhibit very low memory bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve bank-level parallelism, and bank reuse is taken into account only if doing so does not hurt bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8\% and an average execution time reduction of 18.3\%.",
author = "Xulong Tang and Mahmut Kandemir and Praveen Yedlapalli and Jagadish Kotra",
note = "Funding Information: This research is supported in part by NSF grants \#1213052, \#1302557, \#1409095, \#1439021, \#1439057, \#1526750, \#1629915 and \#1629129, and a grant from Intel.; 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016 ; Conference date: 15-10-2016 Through 19-10-2016",
year = "2016",
month = dec,
day = "14",
doi = "10.1109/MICRO.2016.7783760",
language = "English (US)",
series = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
publisher = "IEEE Computer Society",
booktitle = "MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture",
address = "United States",
}