@inproceedings{206f8c59a45a4b22986e1056d37ac2f6,
title = "Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via",
abstract = "This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories on the upper stack. Along with the reconfigurability feature, results show that our SLICE design offers an area reduction of 23% compared to a standard design without reconfiguration capability. Our analysis of FPGA switch box logic and physical design with M3D vias provides insights into the sources of benefits from vertical routing in a multi-stacked design. We also discuss the design overheads involved in incorporating multiple inter-stack vias for better and faster communication among logic routed in different design stacks.",
author = "Srinivasa, {Srivatsa Rangachar} and Karthik Mohan and Chen, {Wei Hao} and Hsu, {Kuo Hsinag} and Xueqing Li and Chang, {Meng Fan} and Gupta, {Sumeet Kumar} and John Sampson and Vijaykrishnan Narayanan",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 ; Conference date: 03-07-2017 Through 05-07-2017",
year = "2017",
month = jul,
day = "20",
doi = "10.1109/ISVLSI.2017.31",
language = "English (US)",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "128--133",
editor = "Ricardo Reis and Mircea Stan and Michael Huebner and Nikolaos Voros",
booktitle = "Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017",
address = "United States",
}