@inproceedings{77c32d56260b4c63b96313f854806d9d,
title = "Improving ILP with instruction-reuse cache hierarchy",
abstract = "Instruction reuse is an interesting strategy for improving processor performance. Several techniques at fine and coarse granularities have been proposed to extend instruction reuse. Among them block and trace reuse are the most promising. This work studies the benefits of combining block and trace reuse with instruction reuse to form an instruction reuse cache hierarchy. A simple reuse hierarchy is implemented and tested with select SPEC95 benchmarks. Both instruction reuse and ILP show modest performance improvements when compared to the base schemes. Within the scope of the selected benchmarks, the proposed reuse policy reuses as much as 60% of possible reusable instructions and shows an average ILP gain of 13.83%. This paper introduces the proposed reuse model and its simulation. The simulation results are presented and analyzed. Finally, future research directions in this area have been discussed.",
author = "D. Charles and Hurson, {A. R.} and N. Vijaykrishnan",
note = "Funding Information: This work in part was supported by NSF Grant MIP 96-22836 and NSF CAREER AWARD CCR-0093085. Publisher Copyright: {\textcopyright} 2002 IEEE.; 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002 ; Conference date: 23-10-2002 Through 25-10-2002",
year = "2002",
doi = "10.1109/ICAPP.2002.1173575",
language = "English (US)",
series = "Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "206--213",
editor = "Wanlei Zhou and Andrzej Goscinski and Guo-jie Li and Xue-bin Chi",
booktitle = "Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002",
address = "United States",
}