TY - GEN
T1 - Improving offset assignment for embedded processors
AU - Atri, Sunil
AU - Ramanujam, J.
AU - Kandemir, Mahmut
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2001.
PY - 2001
Y1 - 2001
N2 - Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in application domains such as signal processing. Given the rapid deployment of these systems, programming on such systems has shifted from assembly language to high-level languages such as C, C++, and Java. The processors used in such systems are usually targeted toward specific application domains, e.g., digital signal processing (DSP). As a result, these embedded processors include application-specific instruction sets, complex and irregular data paths, etc., thereby rendering code generation for these processors difficult. In this paper, we present new code optimization techniques for embedded fixed point DSP processors which have limited on-chip program ROM and include indirect addressing modes using post-increment and decrement operations. We present a heuristic to reduce code size by taking advantage of these addressing modes. Our solution aims at improving the offset assignment produced by Liao et al.’s solution. It finds a layout of variables in RAM, so that it is possible to subsume explicit address register manipulation instructions into other instructions as a post-increment or post-decrement operation. Experimental results show the effectiveness of our solution.
AB - Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in application domains such as signal processing. Given the rapid deployment of these systems, programming on such systems has shifted from assembly language to high-level languages such as C, C++, and Java. The processors used in such systems are usually targeted toward specific application domains, e.g., digital signal processing (DSP). As a result, these embedded processors include application-specific instruction sets, complex and irregular data paths, etc., thereby rendering code generation for these processors difficult. In this paper, we present new code optimization techniques for embedded fixed point DSP processors which have limited on-chip program ROM and include indirect addressing modes using post-increment and decrement operations. We present a heuristic to reduce code size by taking advantage of these addressing modes. Our solution aims at improving the offset assignment produced by Liao et al.’s solution. It finds a layout of variables in RAM, so that it is possible to subsume explicit address register manipulation instructions into other instructions as a post-increment or post-decrement operation. Experimental results show the effectiveness of our solution.
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U2 - 10.1007/3-540-45574-4_11
DO - 10.1007/3-540-45574-4_11
M3 - Conference contribution
AN - SCOPUS:84958745098
SN - 3540428623
SN - 9783540455745
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 158
EP - 172
BT - Languages and Compilers for Parallel Computing - 13th International Workshop, LCPC 2000, Revised Papers
A2 - Ferrante, Jeanne
A2 - Midkiff, Samuel P.
A2 - Moreira, Jose E.
A2 - Gupta, Manish
A2 - Chatterjee, Siddhartha
A2 - Prins, Jan
A2 - Pugh, William
A2 - Tseng, Chau-Wen
PB - Springer Verlag
T2 - 13th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2000
Y2 - 10 August 2000 through 12 August 2000
ER -