Abstract
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.
Original language | English (US) |
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Article number | 2A.2 |
Pages (from-to) | 107-110 |
Number of pages | 4 |
Journal | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
State | Published - Dec 1 2004 |
Event | ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States Duration: Nov 7 2004 → Nov 11 2004 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Science Applications
- Computer Graphics and Computer-Aided Design