In-network caching for chip multiprocessors

Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut Kandemir, Sri Hari Krishna Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


Effective management of data is critical to the performance of emerging multi-core architectures. Our analysis of applications from SpecOMP reveal that a small fraction of shared addresses correspond to a large portion of accesses. Utilizing this observation, we propose a technique that augments a router in a on-chip network with a small data store to reduce the memory access latency of the shared data. In the proposed technique, shared data from read response packets that pass through the router are cached in its data store to reduce number of hops required to service future read requests. Our limit study reveals that such caching has the potential to reduce memory access latency on an average by 27%. Further, two practical caching strategies are shown to reduce memory access latency by 14% and 17% respectively with a data store of just four entries at 2.5% area overhead.

Original languageEnglish (US)
Title of host publicationHigh Performance Embedded Architectures and Compilers - Fourth International Conference, HiPEAC 2009, Proceedings
Number of pages16
StatePublished - 2009
Event4th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009 - Paphos, Cyprus
Duration: Jan 25 2009Jan 28 2009

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5409 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other4th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • General Computer Science


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