TY - GEN
T1 - In-Situ Encrypted NAND FeFET Array for Secure Storage and Compute-in-Memory
AU - Zhao, Zijian
AU - Xu, Yixin
AU - Read, James
AU - Hsu, Po Kai
AU - Qin, Yixin
AU - Huang, Tzu Jung
AU - Lim, Suhwan
AU - Kim, Kijoon
AU - Kim, Kwangsoo
AU - Kim, Wanki
AU - Ha, Daewon
AU - Kampfe, Thomas
AU - George, Sumitha
AU - Gong, Xiao
AU - Datta, Suman
AU - Yu, Shimeng
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - In this work, we present a lightweight in-situ encryption/decryption technique for high-density NAND memory, aiming to meet the growing need for data privacy and security in storage and computing applications. Using ferroelectric FET (FeFET) as a technology platform for demonstration, we show that: i) using a XOR-based cipher, the encryption/decryption can be simply mapped to in-situ array operations, where the encrypted cipher texts are stored as complementary threshold voltage (VTH) states of two consecutive FeFETs in a NAND string and decryption can be simply realized through read operations with key-dependent read gate biases; ii) the proposed technique is scalable to multi-level cells (MLC) by encrypting and decrypting bit-by-bit, thereby significantly increasing the encrypted memory density; iii) a unique advantage of applying XOR-based cipher on NAND array is its capability of supporting high-density and secure compute-in-memory (CiM) (e.g., matrix vector multiplication) with encrypted weights, which is beyond the capability of conventional advanced encryption standard (AES) engine; iv) with integrated NAND FeFET array, we have successfully demonstrated encryption and decryption operations of single-level cell (SLC), MLC, and CiM, showing great promise of the technique.
AB - In this work, we present a lightweight in-situ encryption/decryption technique for high-density NAND memory, aiming to meet the growing need for data privacy and security in storage and computing applications. Using ferroelectric FET (FeFET) as a technology platform for demonstration, we show that: i) using a XOR-based cipher, the encryption/decryption can be simply mapped to in-situ array operations, where the encrypted cipher texts are stored as complementary threshold voltage (VTH) states of two consecutive FeFETs in a NAND string and decryption can be simply realized through read operations with key-dependent read gate biases; ii) the proposed technique is scalable to multi-level cells (MLC) by encrypting and decrypting bit-by-bit, thereby significantly increasing the encrypted memory density; iii) a unique advantage of applying XOR-based cipher on NAND array is its capability of supporting high-density and secure compute-in-memory (CiM) (e.g., matrix vector multiplication) with encrypted weights, which is beyond the capability of conventional advanced encryption standard (AES) engine; iv) with integrated NAND FeFET array, we have successfully demonstrated encryption and decryption operations of single-level cell (SLC), MLC, and CiM, showing great promise of the technique.
UR - http://www.scopus.com/inward/record.url?scp=85185584638&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85185584638&partnerID=8YFLogxK
U2 - 10.1109/IEDM45741.2023.10413774
DO - 10.1109/IEDM45741.2023.10413774
M3 - Conference contribution
AN - SCOPUS:85185584638
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2023 International Electron Devices Meeting, IEDM 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 International Electron Devices Meeting, IEDM 2023
Y2 - 9 December 2023 through 13 December 2023
ER -