Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

Kaisheng Ma; Huichu Liu; Yang Xiao; Yang Zheng; Xueqing Li; Sumeet Kumar Gupta; Yuan Xie; Vijaykrishnan Narayanan

doi:10.1109/ISVLSI.2014.25

Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

Kaisheng Ma, Huichu Liu, Yang Xiao, Yang Zheng, Xueqing Li, Sumeet Kumar Gupta, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

In this paper, two novel 6T SRAM cells based on Independently-Controlled-Gate FinFETs are proposed. The new 6T cells are derived from 4T cells: by separating the read timing and read-line, the proposed new cells allow simultaneously read & write to different addresses. To overcome the traditional retention time problem in 4T cells, the proposed cells reduce leakage by changing the back-gate connection and increasing the capacitance at data storage points (Q, QB). Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed. In addition, this structure is scalable for multi-ports.

Original language	English (US)
Title of host publication	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Publisher	IEEE Computer Society
Pages	296-301
Number of pages	6
ISBN (Electronic)	9781479937639
DOIs	https://doi.org/10.1109/ISVLSI.2014.25
State	Published - Sep 18 2014
Event	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014

Other

Other	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/Territory	United States
City	Tampa
Period	7/9/14 → 7/11/14

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ISVLSI.2014.25

Cite this

Ma, K., Liu, H., Xiao, Y., Zheng, Y., Li, X., Gupta, S. K., Xie, Y., & Narayanan, V. (2014). Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI (pp. 296-301). Article 6903379 IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2014.25

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title = "Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed",

abstract = "In this paper, two novel 6T SRAM cells based on Independently-Controlled-Gate FinFETs are proposed. The new 6T cells are derived from 4T cells: by separating the read timing and read-line, the proposed new cells allow simultaneously read & write to different addresses. To overcome the traditional retention time problem in 4T cells, the proposed cells reduce leakage by changing the back-gate connection and increasing the capacitance at data storage points (Q, QB). Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed. In addition, this structure is scalable for multi-ports.",

author = "Kaisheng Ma and Huichu Liu and Yang Xiao and Yang Zheng and Xueqing Li and Gupta, {Sumeet Kumar} and Yuan Xie and Vijaykrishnan Narayanan",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 ; Conference date: 09-07-2014 Through 11-07-2014",

year = "2014",

month = sep,

day = "18",

doi = "10.1109/ISVLSI.2014.25",

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booktitle = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

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Ma, K, Liu, H, Xiao, Y, Zheng, Y, Li, X, Gupta, SK, Xie, Y & Narayanan, V 2014, Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed. in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI., 6903379, IEEE Computer Society, pp. 296-301, 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, United States, 7/9/14. https://doi.org/10.1109/ISVLSI.2014.25

Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed. / Ma, Kaisheng; Liu, Huichu; Xiao, Yang et al.
Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. IEEE Computer Society, 2014. p. 296-301 6903379.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Ma, Kaisheng

AU - Liu, Huichu

AU - Xiao, Yang

AU - Zheng, Yang

AU - Li, Xueqing

AU - Gupta, Sumeet Kumar

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AU - Narayanan, Vijaykrishnan

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N2 - In this paper, two novel 6T SRAM cells based on Independently-Controlled-Gate FinFETs are proposed. The new 6T cells are derived from 4T cells: by separating the read timing and read-line, the proposed new cells allow simultaneously read & write to different addresses. To overcome the traditional retention time problem in 4T cells, the proposed cells reduce leakage by changing the back-gate connection and increasing the capacitance at data storage points (Q, QB). Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed. In addition, this structure is scalable for multi-ports.

AB - In this paper, two novel 6T SRAM cells based on Independently-Controlled-Gate FinFETs are proposed. The new 6T cells are derived from 4T cells: by separating the read timing and read-line, the proposed new cells allow simultaneously read & write to different addresses. To overcome the traditional retention time problem in 4T cells, the proposed cells reduce leakage by changing the back-gate connection and increasing the capacitance at data storage points (Q, QB). Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed. In addition, this structure is scalable for multi-ports.

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Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

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