Influence of leakage reduction techniques on delay/leakage uncertainty

Yuh Fang Tsai; Vijaykrishnan Narayanan; Yuan Xie; Mary Jane Irwin

Influence of leakage reduction techniques on delay/leakage uncertainty

Yuh Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin

Research output: Contribution to journal › Conference article › peer-review

Abstract

One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V _dd/V _th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.

Original language	English (US)
Pages (from-to)	374-379
Number of pages	6
Journal	Proceedings of the IEEE International Conference on VLSI Design
State	Published - Dec 1 2005
Event	18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India Duration: Jan 3 2005 → Jan 7 2005

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

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abstract = "One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V dd/V th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.",

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year = "2005",

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journal = "Proceedings of the IEEE International Conference on VLSI Design",

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AU - Tsai, Yuh Fang

AU - Narayanan, Vijaykrishnan

AU - Xie, Yuan

AU - Irwin, Mary Jane

PY - 2005/12/1

Y1 - 2005/12/1

N2 - One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V dd/V th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.

AB - One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V dd/V th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.

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M3 - Conference article

AN - SCOPUS:27944460390

SN - 1063-9667

SP - 374

EP - 379

JO - Proceedings of the IEEE International Conference on VLSI Design

JF - Proceedings of the IEEE International Conference on VLSI Design

T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems

Y2 - 3 January 2005 through 7 January 2005

ER -

Influence of leakage reduction techniques on delay/leakage uncertainty

Abstract

All Science Journal Classification (ASJC) codes

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