TY - JOUR
T1 - Input sensitive high-level power analysis
AU - Hezavei, J.
AU - Vijaykrishnan, N.
AU - Irwin, M. J.
AU - Kandemir, M.
AU - Duarte, D.
PY - 2001
Y1 - 2001
N2 - In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.
AB - In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.
UR - http://www.scopus.com/inward/record.url?scp=0035156676&partnerID=8YFLogxK
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U2 - 10.1109/SIPS.2001.957341
DO - 10.1109/SIPS.2001.957341
M3 - Article
AN - SCOPUS:0035156676
SN - 1520-6130
SP - 149
EP - 156
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ER -