Input sensitive high-level power analysis

J. Hezavei; N. Vijaykrishnan; M. J. Irwin; M. Kandemir; D. Duarte

doi:10.1109/SIPS.2001.957341

Input sensitive high-level power analysis

J. Hezavei
, N. Vijaykrishnan
, M. J. Irwin
, M. Kandemir
, D. Duarte

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.

Original language	English (US)
Pages (from-to)	149-156
Number of pages	8
Journal	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
DOIs	https://doi.org/10.1109/SIPS.2001.957341
State	Published - 2001

All Science Journal Classification (ASJC) codes

Media Technology
Signal Processing

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10.1109/SIPS.2001.957341

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title = "Input sensitive high-level power analysis",

abstract = "In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2\% as compared to HSPICE, while running 27 times faster.",

author = "J. Hezavei and N. Vijaykrishnan and Irwin, \{M. J.\} and M. Kandemir and D. Duarte",

year = "2001",

doi = "10.1109/SIPS.2001.957341",

language = "English (US)",

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journal = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

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AU - Vijaykrishnan, N.

AU - Irwin, M. J.

AU - Kandemir, M.

AU - Duarte, D.

PY - 2001

Y1 - 2001

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AB - In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.

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JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

ER -

Input sensitive high-level power analysis

Abstract

All Science Journal Classification (ASJC) codes

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