Instruction scheduling based on energy and performance constraints

A. Parikh; Mahmut Kandemir; Vijaykrishnan Narayanan; Mary Jane Irwin

doi:10.1109/IWV.2000.844527

Instruction scheduling based on energy and performance constraints

A. Parikh, Mahmut Kandemir, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. The results obtained show that these techniques are quite successful in reducing energy consumption and their performance is comparable to that of a pure performance-oriented scheduling.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Workshop on VLSI 2000
Subtitle of host publication	System Design for a System-on-Chip Era, IWV 2000
Editors	Hugo De Man, Asim Smailagic, Robert Brodersen
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	37-42
Number of pages	6
ISBN (Electronic)	0769505341, 9780769505343
DOIs	https://doi.org/10.1109/IWV.2000.844527
State	Published - Jan 1 2000
Event	IEEE Computer Society Workshop on VLSI, IWV 2000 - Orlando, United States Duration: Apr 27 2000 → Apr 28 2000

Publication series

Name	Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000

Other

Other	IEEE Computer Society Workshop on VLSI, IWV 2000
Country/Territory	United States
City	Orlando
Period	4/27/00 → 4/28/00

All Science Journal Classification (ASJC) codes

General Computer Science

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/IWV.2000.844527

Cite this

Parikh, A., Kandemir, M., Narayanan, V., & Irwin, M. J. (2000). Instruction scheduling based on energy and performance constraints. In H. De Man, A. Smailagic, & R. Brodersen (Eds.), Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000 (pp. 37-42). Article 844527 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWV.2000.844527

Parikh, A. ; Kandemir, Mahmut ; Narayanan, Vijaykrishnan et al. / Instruction scheduling based on energy and performance constraints. Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. editor / Hugo De Man ; Asim Smailagic ; Robert Brodersen. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 37-42 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000).

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Parikh, A, Kandemir, M , Narayanan, V & Irwin, MJ 2000, Instruction scheduling based on energy and performance constraints. in H De Man, A Smailagic & R Brodersen (eds), Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000., 844527, Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000, Institute of Electrical and Electronics Engineers Inc., pp. 37-42, IEEE Computer Society Workshop on VLSI, IWV 2000, Orlando, United States, 4/27/00. https://doi.org/10.1109/IWV.2000.844527

Instruction scheduling based on energy and performance constraints. / Parikh, A.; Kandemir, Mahmut ; Narayanan, Vijaykrishnan et al.
Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. ed. / Hugo De Man; Asim Smailagic; Robert Brodersen. Institute of Electrical and Electronics Engineers Inc., 2000. p. 37-42 844527 (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

PY - 2000/1/1

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N2 - Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. The results obtained show that these techniques are quite successful in reducing energy consumption and their performance is comparable to that of a pure performance-oriented scheduling.

AB - Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. The results obtained show that these techniques are quite successful in reducing energy consumption and their performance is comparable to that of a pure performance-oriented scheduling.

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Parikh A, Kandemir M , Narayanan V, Irwin MJ. Instruction scheduling based on energy and performance constraints. In De Man H, Smailagic A, Brodersen R, editors, Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 37-42. 844527. (Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000). doi: 10.1109/IWV.2000.844527

Instruction scheduling based on energy and performance constraints

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All Science Journal Classification (ASJC) codes

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